In order to follow the Moore's law, dual gate transistors have been developed by existing semiconductor technologies. In a dual gate transistor, a channel is surrounded by two gates. The electric current in a dual gate transistor may be doubly controlled, thus the operating speed may be enhanced, the size may be reduced, and the power consumption may be lowered.
FIG. 1 illustrates an existing dual gate transistor. The dual gate transistor includes a substrate having a semiconductor substrate 101, a buried isolator 102, a back gate layer 103, a back gate dielectric layer 104, and a single crystal semiconductor layer 105. The dual gate transistor also includes a top gate dielectric layer 107, a top gate 108, a capping layer 120, and a sidewall spacer 111. The semiconductor substrate 101, the buried isolator 102, the back gate layer 103, and the back gate dielectric layer 104 may form a back gate structure. The top gate dielectric 107, the top gate 108, the capping layer 120, and the sidewall spacer 111 may form a top gate structure.
With the continuous development of the transistor technology, performance requirements of transistors have been increasing, thus how to increase the electron mobility of the channel of a transistor may be an urgent task for the semiconductor industry. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.